VHDL FPGA/CPLD basic level

Profile of participants:

The training is addressed to engineers, designers, developers, IT scpecialists, electronics, automation, ambitious students of technical and hobbyist electronics / IT.

Basic knowledge of digital technology is required. Combinational circuits and software developimng in C / C ++, Basic, Pascal, or any Assembler theory or practical knowledge.

Training purpose

The course aims at the acquisition of knowledge that allows engineers to start working independently in the design of digital circuits in VHDL, both individually and in complex projects developed by teams of engineers-designers.

The training includes practical and theoretical knowledge in the field of VHDL in terms of its use for the development of advanced digital projects, systems based on reprogrammable FPGA and CPLD.

Training program

Training is based on free VHDL simulators: Aldec Active-HDL and ModelSim, sufficient to to cover the training essential. Both tools are recognized in the world of VHDL as a kind of “industry standards”.

Type of training:

Option I – 4 day training
Option II – 4 day training + additional day (with workshop)

Tools and technologies:

Training is based on VHDL simulators free: Aldec Active-HDL and ModelSim sufficient to address the issues covered in the training essential. Both tools are recognized in the world of VHDL as a kind of “industry standards”.

The price of the training includes:

training materials, stationery, deliver equipment and software necessary to implement the exercise. For training in the city of Szczecin, we also provide catering for the duration of training and the drinks (coffee, tea).